Toshiba Information Systems (Japan) Corporation

Layout Design Overview

Best layout using the latest EDA technology [Layout design and verification]

The process for finer patterns enables higher performance and more functions, causing SoC to be larger in scale and more complex. The difficulty in timing closure is a factor in longer development periods. Toshiba Information Systems employs the latest EDA technology to properly deal with issues including signal integrity.


  • Decision on the layout, which is most important for timing closure
  • Layout for timing closure and proper clock processing
  • Implementation of wiring in consideration of crosstalk and measures against IR drop
  • Actions for low energy consumption technology
  • Actions to build technique for multiple power supply by mounting analog IP
  • Actions for DFM (Design For Manufacturing)

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